An array substrate of a conventional display device generally comprises a base substrate and a plurality of parallel gate lines and a plurality of data lines vertically crossed with and electrically insulated from the gate lines, which are disposed on the inside of the base substrate. Two adjacent gate lines and two adjacent data lines are combined to define a pixel unit. Each pixel unit surrounded by two adjacent gate lines and two adjacent data lines includes a thin-film transistor (TFT) configured to drive for image display and a pixel electrode connected with the TFT.
Taking a TFT of a pixel unit in a bottom-gate structure as an example, as illustrated in FIG. 1, a TFT 10 of a pixel unit comprises: a gate electrode 10A disposed on a base substrate and connected with a gate line 20 of the pixel unit; an active layer 10B disposed on the gate electrode 10A; and a source electrode 10C and a drain electrode 10D disposed on the active layer 10B and respectively disposed on two sides of the active layer 10B, wherein the source electrode 10C is a portion of a data line 30 disposed in an overlapped area between the active layer 10B and the data line 30 of the pixel unit; the drain electrode 10D is partially overlapped with the active layer 10B and connected with a pixel electrode 50 of the pixel unit via a through hole 40; the gate electrode 1A, the active layer 10B and the source electrode 10C are rectangular; the gate electrode 10A completely covers the active layer 10B which completely covers the source electrode 10C; the drain electrode 10D is “P”-shaped; an overlapped area between the drain electrode 10D and the active layer 10B is rectangular; if the direction along the data line 30 is taken as the width direction, the width value of the overlapped area between the drain electrode 10D and the active layer 10B, the width value of the source electrode 10C and the width value of the active layer 10B are equal to each other and all are “w”; the width value of the gate electrode 10A is “a”; and the width value of the drain electrode 10D is “b,” where w<a<b.
Currently, as for a pixel unit, a black matrix (BM) for light shielding is usually disposed on gate lines, data lines and a TFT of the pixel unit. As illustrated in FIG. 1, the black matrix covers gate lines 20, data lines 30, the gate electrode 10A, the active layer 10B, the source electrode 10C and the drain electrode 10D. If the vertical direction is taken as the width direction, supposing that a pixel unit is 60 micrometers in width and 20 micrometers in length, as illustrated in FIG. 1, the width value “c” of areas of the black matrix covering the TFT 10 of the pixel unit generally can reach 28 micrometers. That is to say, the coverage area of the black matrix in each pixel unit is relatively large, so the light transmittance is relatively low, and hence the brightness of the display screen of a display device is relatively low.